1. Field
The present disclosure relates generally to high-speed data communications interfaces, and more particularly, signal conditioning in multi-wire, multi-phase data communication links.
2. Background
Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while the display for the cellular phone may be obtained from a second manufacturer. The application processor and a display or other device may be interconnected using a standards-based or proprietary physical interface. For example, a display may provide an interface that conforms to the Display System Interface (DSI) standard specified by the Mobile Industry Processor Interface Alliance (MIPI).
In a multi-wire interface, the maximum speed of the communication link and the ability of a clock-data recovery (CDR) circuit to recover clock information may be limited by the maximum time variation related to transitions of signals transmitted on the communication link. In a multi-wire interface, transitions on different wires may exhibit different variations of signal transition times, which can cause the outputs of receivers in a receiving device to change at different times with respect to a data or symbol boundary. Large transition time differences in multi-wire signals often requires the implementation of a delay element in the CDR circuit, where the delay element has a minimum delay at least as long as the difference between the min and max receiver transition events. The maximum time of this delay element can restrict the throughput on the communication link by significantly limiting the period of the transmission clock.